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Prijs
Up To €10 (0) € 10 Tot € 20 (0) € 20 Tot € 50 (0) € 50 En Meer (1)
Auteur
Sutherland, Stuart (1) Fpga Conference Committee (2) Fpga 16 Conference Committee (1) Taylor, Adam, Binnun, Dan, Srivastava, Saket (1) Roy, Shirshendu (1)
Verschijningsdatum
2017 (1)
Bindwijze
Overig (1)

Resultaat

Sutherland, Stuart - RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Paperback
Sutherland, Stuart
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
€ 123.70
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